DINO CPU Assignments (for ECS 154B)

In this course, you will be implementing the Davis IN-Order CPU (DINO CPU) design in Chisel, a high-level hardware description language.

DINO CPU documentation

See the GitHub Repository for high-level details about the DINO CPU project and how to contribute.

You can find documentation in the DINO CPU repository.

Chisel notes goes through an introduction to Chisel and how to create hardware.

The Chisel cheat sheet is particularly useful for the projects.

There’s also a list of common errors that you may run into while working on the DINO CPU.

Finally, for debugging, the documentation on Single stepping will be very useful.

Assignments/Projects

Assignment 1: Getting started with Chisel DUE 1/19

In this assignment, we will introduce you to the Chisel “hardware construction language” by asking you to implement a couple of simple circuits in Chisel. First, you will implement the ALU control unit that you will use in the single cycle CPU design. Then, you will begin implementing the single-cycle CPU datapath. By the end of this assignment you will be able to correctly execute 28 RISC-V instructions (about 37%)!

Assignment 2: A single-cycle CPU design DUE 1/29

In this assignment, you will extend what you started in assignment 1 and implement the rest of the RISC-V RV64IM instruction set! To do this, you will complete the datapath implementation and implement the control logic for the processor. At the end, you will be able to run real applications compiled with GCC on your processor!

Assignment 3: A pipelined CPU design DUE 2/16

In this assignment, broken into two parts, you will be implementing a more realistic, pipelined-based core design. In the first part, you will split your single cycle design into five different pipeline stages and ensure that all instructions except control have a correctly wired datapath. Then, in part two you will finish wiring the rest of the datapath and the control path for the control instructions and implement the hazard detection and forwarding logic.

Assignment 4: TBD DUE 3/1

TBD

Assignment 5: Parallel architecture with gem5 DUE 3/15

Instead of doing another DINO CPU assignment, you will be using gem5 for this assignment. Since parallel systems are very complex, I can’t expect you to be able to design a working system in Chisel. However, gem5 already has all of the models necessary to run a full-fledged parallel system (it can even boot Linux!). So, we’ll be using gem5 and doing the same assignment as ECS 201A.

Discussions

DINOCPU Videos

You will find video tutorials and examples on the DINOCPU Spring 2020 project here.

All videos will be hosted on the UC Davis Aggie video platform.

• Basics
  • Setup
  • Chisel Example
  • Single-Stepper Example
• Pipelined
  • Bubbles vs Stalls

Setup

In this video, we cover setup for remote connections to the CSIF machines using VSCode and cloning of the DINOCPU project.

In this video, we will talk about how to setup and use github Codespace for the DINOCPU assignments.

Chisel Example

In this video, we cover a simple Chisel example to highlight the basic syntax and project workflow.

Single-Stepper Example

In this video, we cover how to use the Single-Stepper to debug your DINOCPU implementations.

Bubbles vs Stalls

In this video, we cover the differences of flushing and stalling, as well as an example of a bubble moving through the pipelined DINOCPU project.

---