Processor Architecture

In this section of the course, we will learn details of how to design a processor core. The processor core is the “brain” of the computing system. It reads in (fetches) instructions from memory, figures out what the instruction is supposed to do (decodes it), and performs the task(s) of the instruction (executes it).

ISA and Machine Representation

We will begin with what should be a review of ISAs and machine representation of instructions. These topics were covered mostly in ECS 50. However, we will be using the RISC-V open source ISA. If you did not take ECS 50 or find yourself struggling to keep up in this first set of lectures, please refer to Chapter 2 in Computer Organization and Design.

• What is an ISA?
  • RISC vs CISC
  • QUIZ ISAs and RISC vs CISC
• RISC-V
  • Question: “Why 7 bits for the opcode?”
• Machine code examples
  • add example
  • lw example
  • Optional further reading: Compiling, linking, and assembling
• QUIZ RISC-V and machine representation

Assignment 1 DUE 1/17

See Machine code examples VIDEO for some helpful hints.

Single cycle processor design

Next, we will talk about how to design a single-cycle CPU. This design will use combinational logic to do all of the steps to complete an instruction in a single cycle. Assignment 1 and Assignment 2 have you implement this design in Chisel. This design is covered in Section 4.3 and 4.4 of Computer Organization and Design.

• Steps to execute an instruction
• Data path and control path
• QUIZ Single cycle design
• Performance and limits to a single cycle design
  • Performance of the single cycle design
  • How to improve this design and single cycle limitations
  • QUIZ The Single cycle design’s performance

Assignment 2 DUE 1/24

Pipelined processor design

After covering the basics of processor design, we will start optimizing this design to try to get better performance and come closer to how real systems like the one pictured above is designed. Our first optimization will be adding pipelining to our design. This is covered in Section 4.5 and 4.6 of Computer Organization and Design and is the basis for Assignment 3.

• Basic pipeline design
  • What is pipelining?
  • Pipelined design for the DINO CPU
  • Example execution in pipelined DINO CPU
  • Pipelined CPU performance
  • QUIZ Basic pipelining
• Pipeline hazards
  • Limits of our basic pipelined design and data hazards
  • How to handle data hazards (forwarding)
  • QUIZ Data hazards
  • Control hazards and branch prediction
  • Other kinds of hazards: Structural hazards
• Exceptions in a pipelined processor
• Putting it all together: examples of pipelined execution
  • QUIZ Pipelining review

Instruction level parallelism

Finally, we will introduce the idea of instruction level parallelism and introduce a couple of algorithms that can be used to extract performance from scalar (not parallel) applications. Most of this topic is covered in the graduate level computer architecture course (ECS 201A), but we will touch on some of these topics in this class.

• Static ILP
  • Instruction scheduling
  • A new ISA type: VLIW
  • QUIZ Static scheduling
• Dynamic ILP
  • Dynamic instruction scheduling
• Register renaming
  • QUIZ Dynamic ILP

Test

Date: 2/8. More information to follow.

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