Parallel Memory Systems

Cache coherence and memory consistency

These two topics are near and dear to my heart. I’ve spent the last 10 years of my life working on these topics. The next 20 minutes of lecture don’t do them justice at all. If you’re interested to know more, there’s a great book by my former advisors: A Primer on Memory Consistency and Cache Coherence. I could teach a whole course just on that book! (Note: if you’re on campus or use a campus VPN, you can download the PDF for free.)

Cache coherence

This video discusses what happens with the previous barrier example when we add caches to the system.

This video goes into the detail of one cache coherence protocol implementation that has three states: Modified, shared, and invalid or MSI.

Memory consistency

While coherence ensures that caches stay transparent to the programmer, the memory consistency model is actually something that’s part of the ISA and defines how the programmer should expect multi-threaded programs to behave. Another way of looking at this is that cache coherence defines what happens to a single address (e.g., the single-writer multi-reader invariant) whereas memory consistency defines the behavior when multiple addresses are involved.

This video introduces the idea of memory consistency and talks about the importance of a fence instruction.

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