ISAs and Machine Representation

We will begin with what should be a review of ISAs and machine representation of instructions. These topics were covered mostly in ECS 50. However, we will be using the RISC-V open source ISA. If you did not take ECS 50 or find yourself struggling to keep up in this first set of lectures, please refer to Chapter 2 in Computer Organization and Design.

What is an ISA?

First, let’s start by discussing what is the architecture? In the video below, I describe the different parts of the computing stack and how the architecture defines how the software and hardware interacts.

If you’re interested in the details of the three ISAs I mentioned in the above video you can follow the links for the ISA manuals for RISC-V (github link), Intel X86, and ARM.

With that introduction to architecture and ISAs, let’s now dig a little deeper into what is exactly is the “ISA”.

RISC vs CISC

Callback to the Turing Lecture. From 13:08-16:40 talks about why we moved from CISC ISAs to RISC ISAs. You can (optionally) read a blog post that Dave Patterson wrote which gives some more background on this fundamental change in computer architecture.

Below, I talk more about the difference between “RISC” and “CISC” machines and how this is another example of how technology changed, so the “best” way to design a computer also changed.

QUIZ ISAs and RISC vs CISC

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RISC-V

In this class, we will be using the 32-bit RISC-V ISA. Specifically, we’ll be using the rv32i variant of RISC-V. You can find all of the details about the RISC-V ISA in the RISC-V Specification document.

You can find the instructions that we care about, the 32-bit integer instructions, in the opcode table. Note that this quarter (Winter 2024), the 154B class will be implementing the 64-bit version of the RISC-V integer ISA. Very little changes from what is discussed below. Details of the 64-bit ISA are covered in the book, and in the RISC-V Reader.

The main differences are:

1. The register file is 64 bits wide
2. There are a few extra instructions to implement (wider shift instructions and loads and stores).

These two videos (I got tired after the first one) discuss some details of the RISC-V ISA and give a quick example of a small RISC-V program. More details are available in Chapter 2 of Computer Organization and Design, Section A.9 in A Quantitative Approach and the RISC-V Reader.

Question: “Why 7 bits for the opcode?”

There was a great question on from a student in Spring Quarter 2020. They asked,

From my understanding, the opcode of an instruction specifies what type of instruction it is or what the instruction does. My question is why is the opcode 7 bits wide (representing 2^7=128 possible operations) when there are only 47 types of instructions in the RISC-V table here. In this table there are much less than 128 unique opcodes. Couldn’t we use less bits to represent the opcode? What occurs if a value of say 0b1111111 (which isn’t in the table) happens to be the value of the opcode?

Here’s my answer!

Machine code examples

Finally, let’s put this all together and look at how an instruction is executed on a simple processor (this is an intro to the next section). These two videos go through two different full examples of decoding and executing RISC-V instructions. The first video show a simple R-type instruction (add) and the second video a load instruction (lw). Note that the first video’s add example is basically the answer to the question in assignment 1.

add example

lw example

Optional further reading: Compiling, linking, and assembling

QUIZ RISC-V and machine representation

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